The present invention relates generally to analog-to-digital converters, and specifically to analog-to-digital converters having folded differential logic encoding architectures.
As speeds of operation of electronic equipment increase, analog-to-digital converters (ADCs) need to operate at increasing rates in order not become a bottleneck in the operation of the equipment. A known architecture in the electronic art, which inherently comprises a fast system for analog-to-digital conversion, is xe2x80x9cflashxe2x80x9d architecture, wherein a number of comparators operate simultaneously and in parallel. The readout of a flash ADC is substantially a xe2x80x9cone-stepxe2x80x9d process.
FIG. 1 is a schematic block diagram of an m-bit flash analog-to-digital converter (ADC) 10, as is known in the art. Flash ADC 10 comprises a series resistor ladder 12, having 2m equal valued resistors coupled to a first reference voltage Vr1 and a second reference voltage Vr2, which generate 2m sequential potentials. The potentials are respectively applied to a first input of 2m comparators 14, which have a voltage Vin to be digitized applied to a second input of the comparators. The output of the comparators is in the form of thermometer code, which is converted to binary code by a decoder 16. Decoder 16 typically uses conversion from thermometer code to Gray code as an intermediate step, in order to reduce the effects of sparkles and meta-stability in the thermometer code. ADC 10 is typically implemented as a very large scale integrated circuit (VLSI).
FIG. 2 is a schematic electronic diagram of a 3-bit ADC 20 using a folded differential logic (FDL) architecture, and giving a Gray code output, as is known in the art. A series ladder 21, which is driven by reference potentials Vr1 and Vr2, and an analog voltage input line 23 provide input levels to comparators 22A, 22B, . . . , 22G. Thermometer code outputs, and their inverses, are generated as differential outputs by the comparators. The differential outputs of comparators 22A, 22B, . . . , 22G are herein termed (T1,{overscore (T1)}), (T2,{overscore (T2)}), . . . , (T7,{overscore (T7)}) respectively. Differential outputs (T1,{overscore (T1)}), (T2,{overscore (T2)}), . . . , (T7,{overscore (T7)}) are input to respective differential pairs of transistors 24A, 24B, . . . , 24G. Each differential pair of transistors is driven by a current source delivering a current I0. As shown in the diagram, the outputs of groups of the differential pairs are added, and the summed outputs generate respective potentials across resistors 25A, 25B, . . . , 25F. The outputs of the differential pairs are connected to comparators 26, 28, and 30, so as to generate Gray code outputs D0, D1, and D2 respectively.
Thus, comparator 26, generating the least significant bit (LSB), receives its potential inputs from current source 32 (delivering a current I0) and differential pairs 24A, 24C, 24E, and 24G feeding through resistors 25E and 25F. Since four differential pairs are summed, comparator 26 has a folding factor of 4. The inputs to comparator 26 are generated on lines 27 and 29, which have a voltage corresponding to T1+{overscore (T3)}+T5+{overscore (T7)}+1 and a voltage corresponding to {overscore (T1)}+T3+{overscore (T5)}+T7 respectively. Thus, comparator 26 forms its output for a value of the LSB by effectively comparing T1+{overscore (T3)}+T5+{overscore (T7)}+1 with {overscore (T1)}+T3+{overscore (T5)}+T7.
Comparator 28 receives its potential inputs from a current source 34 and differential pairs 24B and 24F feeding through resistors 25C and 25D. Since two differential pairs are summed, comparator 28 has a folding factor of 2. The inputs to comparator 28 correspond to T2+{overscore (T6)}+1 and {overscore (T2)}+T6, and the comparator forms its output for a value of a first bit by effectively comparing T2+{overscore (T6)}+1 with {overscore (T2)}+T6. Similarly, comparator 30 has inputs corresponding to T4 and {overscore (T4)}, forming an output for a value of a most significant bit (MSB) by effectively comparing T4 with {overscore (T4)}.
Analog-to-digital converters exemplified by ADC 20 use FDL architecture implemented with bipolar transistors. However, bipolar transistor technology suffers from a number of known disadvantages compared with complementary metal oxide semiconductor (CMOS) technology. For example, bipolar transistors dissipate significantly higher powers and require relatively larger areas of silicon substrate compared with CMOS transistors.
U.S. Pat. No. 6,014,098, to Bult et al., whose disclosure is incorporated herein by reference, describes an ADC implemented in a CMOS technology. Outputs of comparators of the ADC are fed through cascaded stages of averaging amplifiers. The stages comprise folding, so that the cascading effectively implements multiple folding.
In preferred embodiments of the present invention, a folded differential logic (FDL) encoder section of an analog-to-digital converter (ADC) operates by redistributing charges stored within two sub-sections of the encoder. The charges are stored on capacitors, preferably by means of transistors acting as capacitors. The redistribution is implemented by switching logic, preferably implemented by switching transistors. Both types of transistors are most preferably implemented using complementary metal oxide semiconductor (CMOS) technology, although other technologies may also be used to implement the transistors. Operating an FDL encoder by redistributing charges substantially reduces power dissipation, compared to encoders which operate by comparing currents, since there is substantially no current flowing from supply to ground. In addition, rates of operation of charge redistribution encoders are significantly faster, and less area of silicon substrate is required, than in encoders comparing currents. This ADC design is therefore particularly well suited for CMOS implementation.
Within each sub-section of the FDL encoder, a primary capacitor is charged to an initial voltage. Each sub-section receives thermometer code which is produced in a thermometer code generator responsive to an analog input voltage. Within each sub-section the code activates a number of transistor switches, according to a value of the code, which are coupled to secondary capacitors. The charge is thereby redistributed between the primary capacitor and the number of the secondary capacitors that are coupled by the activated switches. The charge redistribution causes a voltage drop from the initial voltage, the drop being a function of the number of secondary capacitors receiving the charge, and thus of the thermometer code. The voltage drops in the two sub-sections are compared to generate an output bit corresponding to the input analog voltage.
Preferably, the ADC comprises a plurality of FDL encoder sections, each encoder section generating a specific bit corresponding to the analog input voltage.
There is therefore provided, according to a preferred embodiment of the present invention, an analog-to-digital converter, including:
a code generator, coupled to receive an input analog voltage and to one or more reference voltages, and adapted to generate a digital code responsive thereto; and
one or more folded differential logic encoders (FDLEs), each of the FDLEs including:
a plurality of capacitors; and
switching logic, coupled to receive the digital code and distribute a charge between the plurality of capacitors responsive to the received digital code, and to output a digital bit indicative of the input analog voltage responsive to a magnitude of a potential generated by the distributed charge on at least one of the plurality of capacitors.
Preferably, the code generator includes a thermometer code generator, and the digital code includes thermometer code.
Preferably, the plurality of capacitors includes one or more primary capacitors and the switching logic includes one or more primary switches coupled to the one or more primary capacitors, which switches are adapted to couple the one or more primary capacitors to receive the charge.
Further preferably, the plurality of capacitors includes one or more secondary capacitors, and the switching logic includes one or more secondary switches coupled to receive the digital code and to connect the one or more secondary capacitors to the one or more primary capacitors responsive to the digital code, so as to distribute the charge between the one or more primary capacitors and the one or more secondary capacitors.
Preferably, the plurality of capacitors includes a first group of capacitors and a second group of capacitors, the switching logic includes a first group of switches and a second group of switches, the potential includes a first potential and a second potential, and at least some of the FDLEs include:
a first sub-section, including the first group of capacitors and the first group of switches, receiving a first part of the digital code and generating the first potential responsive thereto;
a second sub-section, including the second group of capacitors and the second group of switches, receiving a second part of the digital code and generating the second potential responsive thereto; and
a comparator which outputs the digital bit responsive to a comparison of the first and the second potential.
Further preferably, the first part of the digital code is substantially an inverse of the second part of the digital code.
Preferably, the first group of capacitors includes a bias capacitor adapted to incorporate a bias level into the first potential, and the first group of switches includes a bias switch adapted to activate the bias capacitor.
Preferably, at least one of the first and second sub-sections includes one or more dummy circuit elements, so that at least some electrical properties of the first and second sub-sections are substantially similar.
There is further provided according to a preferred embodiment of the present invention, a method for converting an analog input voltage to a digital value, including:
generating a digital code responsive to the input analog voltage and to one or more reference voltages;
responsive to the digital code, distributing a charge between a plurality of capacitors in each of one or more folded differential logic encoders (FDLEs); and
outputting a digital bit indicative of the input analog voltage from each of the one or more FDLEs responsive to a magnitude of a potential generated by the distributed charge therein.
Preferably, the digital code includes thermometer code.
Preferably, the plurality of capacitors includes one or more primary capacitors and distributing the charge includes storing the charge on the one or more primary capacitors.
Preferably, each of the FDLEs includes one or more secondary switches, the plurality of capacitors includes one or more secondary capacitors, and distributing the charge includes:
the one or more secondary switches receiving the digital code; and
connecting the one or more secondary capacitors to the one or more primary capacitors responsive to the digital code via the one or more secondary switches, so as to distribute the charge between the one or more primary capacitors and the one or more secondary capacitors.
Preferably, the plurality of capacitors includes a first group of capacitors and a second group of capacitors, each of the FDLEs includes a first group of switches and a second group of switches, the potential includes a first potential and a second potential, and each of the FDLEs includes a first sub-section, including the first group of capacitors and the first group of switches, and a second sub-section, including the second group of capacitors and the second group of switches, wherein the charge includes a first charge and a second charge, and wherein distributing the charge includes:
receiving a first part of the digital code in the first sub-section;
activating the first group of switches responsive to the first part of the digital code;
distributing the first charge responsive to the first group of activated switches;
generating the first potential responsive to the distributed first charge;
receiving a second part of the digital code in the second sub-section;
activating the second group of switches responsive to the second part of the digital code;
distributing the second charge responsive to the second group of activated switches; and
generating the second potential responsive to the distributed second charge; and
wherein outputting the digital bit includes comparing the first and the second potential.
Preferably, the first part of the digital code is substantially an inverse of the second part of the digital code.
Preferably, the first group of capacitors includes a bias capacitor adapted to incorporate a bias level into the first potential, and the first group of switches includes a bias switch adapted to activate the bias capacitor.
Preferably, at least one of the first and second sub-sections includes one or more dummy circuit elements, so that at least some electrical properties of the first and second sub-sections are substantially similar.